In a conventional Metal oxide semiconductor field effect transistor (MOSFET) or insulated gate bipolar transistor (IGBT), the MOS structures are distributed on one face of the semiconductor substrate to control the main current flowing between two electrodes on opposing faces of the substrate. FIG. 2 shows a part of such an MOS device. The MOSFET structure has p-type channel areas 2, distributed on the surface of the n-type base area 1 of the silicon substrate. The portion of the base area 1 which is exposed in relation to the gate 5, lies between the p-type channel areas 2, forming a p.sup.+ well 3 at the center of the channel area 2. Located at the periphery of the exposed base area is the n.sup.+ source area 4. The gate 5 consists of polycrystal silicon and is generated through the gate oxide film to form the channel in the part between the source area 4 and the base area 1. The source electrode 8, insulated from the gate 5 by the insulating layer 7, is in contact with both the p.sup.+ well 3 and the source area 4.
The p.sup.+ well 3 lowers the contact resistance between the source electrode and the channel area, and makes it more difficult to activate the parasitic NPN transistor consisting of the n.sup.+ source area 4, p-type channel area 2, and n-type base area 1. In this semiconductor device, applying the reverse bias to the PN junction between the n-type base area 1 and the p-type channel area 2, and between the n-type base area 1 and the p.sup.+ well 3, generates a depletion area 10, indicated with a dotted line in FIG. 2. This is accomplished by applying a voltage across the electrode in contact with the n.sup.+ layer on the opposite side of the base area 1, or with the p.sup.+ layer on the outside of the n.sup.+ layer and the source electrode 8. When the reverse bias is sufficiently high, a breakdown occurs in this PN junction, and diffusion in the p.sup.+ well 3 is deeper with respect to the p-type channel area 2. Consequently, avalanche breakdown occurs at the tip of the p.sup.+ well 3. This suppresses current into the parasitic bipolar transistor, or, if that current flows, it is difficult to turn on the transistor because of the low base resistance of the transistor. When the parasitic transistor is activated, although a large current flows through the PN junction lowering the avalanche breakdown strength, the avalanche breakdown strength can be increased since the avalanche breakdown, which occurs at the tip of the p.sup.+ well, makes it more difficult to activate the parasitic NPN transistor.
When diffusion in the p.sup.+ well 3 is deep, the base area must be thick or its resistance high to maintain the avalanche voltage, i.e., the voltage above which breakdown occurs, between the p-type channel area 2 and the n-type base area 1, and between the p.sup.+ well 3 and the n-type base area 1. This causes two problems. One is that the activation resistance (R.sub.DS(ON)) increases when the MOSFET formed on the surface is turned on. The other is that the diffusion time to deepen the diffusion must be longer.